Unit 4
Machine Level Structure, Operation and Assembly Language Programming

Structure of Processor


Full Meaning

Purpose and other details


Arithmetic Logic Unit

Carries out arithmetic and logic operations


Control Unit

Decodes instructions and sends signals to other units/registers/peripherals


Immediate Access Store

Main Memory - stores data and instructions



Special register; storage for one word of data. While in register data can be modified


Sequence Control Register (Program Counter)

Holds address of next instruction to be fetched


Memory Address Register

Holds address of memory location to be read from/written to


Memory Buffer Register
Memory Data Register

Contains word read from/written to memory


Current Instruction Register

Current instruction is held while it is being decoded


Status Register

Holds state of accumulator etc. Bits used to record state of CPU e.g. -ve, carry, overflow, BCD, interrupt disabled


Index Register

Fetch-Execute Cycle

Fetch-execute cycle - complete process of retrieving an instruction from store, decoding it and carrying it out

    Fetch Phase

  1. The address of the next instruction to be executed is copied from the SCR to the MAR
  2. The instruction held at that address is copied to the MDR
  3. Simultaneously the contents of the SCR is incremented so that it holds the address of the next instruction
  4. The contents of the MDR are copied to the CIR

  5. Execute Phase

  6. The instruction held in the CIR is decoded
  7. The instruction is executed


Interrupt - signal from a device or source seeking the attention of the processor

Interrupt register - special register in CPU which is checked at the beginning of each fetch-execute cycle. Each bit represents a different type of interrupt. If a bit is set the state of the current process is saved and OS routes control to appropriate interrupt handler

Interrupt priorities - when two interrupts are received simultaneously, the one with the highest priority is dealt with first

Hardware failure e.g. power failure has the highest priority of interrupt to allow the OS to shut down as gracefully as possible

An I/O device which signals normal completion or that an error has occurred would have the lowest priority

Vectored interrupt mechanism - the interrupting device supplies an offset that is added to the base address. New ISRs can therefore be placed at any appropriate memory location and the interrupting device only need supply the correct offset for the vector to be located.

Von Neumann stored program concept - instructions are fetched and executed one at a time in a serial manner. Data, instructions and addresses are transmitted between memory and the processor along data and address buses. Control bus used to send control and timing signals between various components of CPU and main memory.

Features of processor design which improve processor performance:

Buses - transmit data and instructions between system components

Address bus - the width determines the maximum address that can be directly referenced

Data bus - the width determines how many bits can be transferred simultaneously

Assembly language

Instruction set - set of machine instructions that a processor recognises and can execute

Examples of assembly language instructions:


Load accumulator with contents of specified address


Store contents of accumulator in specified address


Load specified number into accumulator


Add contents of specified address from accumulator


Subtract contents of specified address from accumulator


Add given number to accumulator


Subtract given number from accumulator


Perform Boolean AND


Perform Boolean OR


Jump if accumulator zero


Unconditional jump

Shift Instructions





MSB is discarded as all other bits move to the left

LSB shifted into carry bit & zero moves in to occupy vacated space


Multiply by 2;

Sign bit is preserved

Divide by 2;

Sign bit is preserved, i.e. if sign bit is one, one is moved in from left


MSB is moved into carry bit

Value of carry bit is moved into vacated position

Zero address instruction - does not require operand e.g. HALT

One address instruction - one byte for operand e.g. STA X

Two address instruction - two bytes for operand, either because 2 operands are involved or because the operand is too large to fit into one byte e.g. MOV R1, R2

Addressing modes

Immediate (literal) addressing - operand is the data used

Direct addressing - operand is the address where the data can be found

Indirect addressing - operand is the address of a location which in turn holds the address of the data required

Indexed (modified) addressing - operand is modified by adding the contents of the index register to give an address of the data

Relative addressing - operand contains an offset to a known (or implied) base address e.g. SCR

Base register addressing - operand is added to base address to give address of data